1. Technical Field
The present invention relates generally to electronic design automation, and in particular, to a computer implemented method for selectively reducing pessimism in graph based analysis of integrated circuits.
2. Description of Related Art
Some of the most complicated devices ever engineered by man are semiconductor integrated circuits. Some circuits such as microprocessors may include a billion transistors or more, and are getting more complicated in their design every year. As a result, testing throughout the design and manufacturing processes is necessary to be able to reliably manufacture these semiconductor integrated circuits. This includes testing of circuit designs, testing of layout designs derived from the circuit designs, and testing of the resulting manufactured integrated circuits.
Static timing analysis (STA) is often utilized for performing timing analysis towards validation and optimization of synchronous circuit designs. This allows the designer to make modifications to improve the reliability, efficiency, and/or speed of the circuit design. Pessimism is generally incorporated into STA so that variations in modeling, design and manufacturing are essentially taken into account.
Graph based analysis (GBA) is a type of STA used to perform worst case analysis of a circuit over all possible input combinations and all possible paths, but not of the logical operation of the circuit. GBA uses pessimism to improve the speed of the analysis. For example, GBA utilizes the worst input slew of all input pins through each logic element, but not the logic operation of the circuit.
Path based analysis (PBA) is another type of STA. used to calculates delays beginning at the input and tracing the path to the output. It is generally less pessimistic than GBA, but is much slower in an zing circuit designs as each circuit path analyzed. For example, only the slews of the input pins along a given. circuit path are considered in this analysis.
An implementation, optimization and engineering change order (ECO) process for fixing of a circuit design involves modifying the design to meet timing, power and area goals of the circuit while achieving the desired circuit functionalities. During this process a variety of transforms or other modifications are performed on circuit elements (e.g., gates and registers) and GBA static timing analysis is typically used to measure the circuit performance for timing goals. Since GBA does a worst case analysis, it is more pessimistic than PBA. However, due to the exhaustive nature of PBA and the amount of computational time needed to perform PBA, it is rarely used for optimization and generally only used at final signoff of a circuit design.